The department of Electronics and Communication Engineering organized a webinar on Functional Verification of Complex SoC designs using UVM from 11.00am to 12.30 pm on 20.7.2020. Mr.Reniflal Ebinezar, R&D Division, ASIC/FPGA Design Validation Engineer, Nokia, Belgium was the resource person. Basics of Universal Verification Methodology (UVM), UVM frameworks, different phases and classes in UVM were discussed. A verification procedure of SoC which is not just the processor, but a whole system within a chip was interesting to all the participants. Verifying the Processor IPs with Bare Metal Code in UVM, model based verification was also discussed. This webinar has provided better insights in verification field. Totally 92 participants get benefitted from this programme. Dr.M.Jayasanthi ASP/ECE and Ms.M.Deepa AP(Sr.Gr.) /ECE were the co-coordinators of this programme.