A value added course on VHDL (Very high speed integrated circuit (VHSIC) Hardware Description Language)
using Xilinx ISE was organized by Ms.Vishnupriya A (AP-ECE).It was conducted for
the second year students of Electronics and Communication Engineering department,
during their fourth semester for a period of five weeks. The course covered the basic
building units of digital design (combinational and sequential circuits) using VHDL.
The students were exposed to three different modeling styles: data flow, behavioral
and structural. They also gained the understanding and building skills of VHDL
constructs that can be synthesized into programmable logic device. The course was
an eye opener for a practical approach to VHDL. The duration of the course was
from 28.12.2016 to 11.04.2017. Totally 32 Participants attended the course.
All the below mentioned experiments are simulated in all the 3 modeling styles in VHDL.